(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices and more specifically to a process used to form metal silicide on specific regions of metal oxide semiconductor field effect transistor (MOSFET) devices.
(2) Description of Prior Art
To improve MOSFET device performance metal silicide has been used on source/drain as well as on conductive gate structures. The use of the lower resistance metal silicide, when compared to more resistive non-silicided source/drain regions and polysilicon gate structures, result in he desired resistance—capacitance (RC) values allowing MOSFET performance enhancement to be realized. Candidates for metal silicide include titanium silicide as well as cobalt silicide, however both present shortcomings when used for MOSFET devices that are comprised with shallow source/drain regions and narrow width gate structures. The minimum resistance of titanium silicide is difficult to achieve sometimes necessitating several anneal cycles needed to obtain the low resistance C54 phase, specifically when titanium silicide is formed on the top surface of narrow width conductive gate structures. In addition during the consumption of silicon during metal silicide formation greater silicon consumption is encountered during cobalt silicide formation than experienced with other metal silicide counterparts thus presenting risks when shallow source/drain regions are employed.
Nickel silicide features desirable low resistance as well as consuming only minimal amounts of silicon during formation, however the attainment of nickel silicide can be more difficult to achieve than other metal silicides such as titanium silicide or cobalt silicide. Nickel silicide is unstable at temperatures greater than 750° C., sometimes resulting in an agglomeration phenomena, therefore an anneal procedure performed at these temperatures, applied to a nickel layer directly on a narrow width conductive gate structure can result in unwanted nickel silicide agglomeration. A method used to reduce the anneal temperature needed for nickel silicide formation is the employment of an interlayer material, a material placed between nickel and the underlying areas, a source/drain region as well as the conductive gate structure. An initial phase of an anneal procedure now performed at lower temperatures results in an intermediate silicide layer comprised of nickel and the interlayer material, while a final phase of the same anneal procedure performed with the intermediate silicide layer overlying the MOSFET regions source/drain region, results in the desired nickel silicide layer formed on the source/drain region as well as on the top surface of the conductive gate structure.
A shortcoming of the employment of the interlayer material, allowing nickel silicide to be formed at temperatures below which instability occurs, is the ability to form a thin, less than 20 Angstroms, interlayer material uniformly, and conformally across a semiconductor substrate. The present invention will describe formation of nickel silicide at a temperature in which nickel silicide instability is eliminated via use of a thin interlayer material uniformly obtained via a specific deposition mode. Prior art such as Maa et al, in U.S. Pat. No. 6,468,901 B1, Kaloyeros et al, in U.S. Pat. No. 6,346,477 B1, Lowery et al, in U.S. Pat. No. 6,511,867,B2, and Grant et al, in U.S. Pat. No. 6,423,619 B1, describe methods of forming MOSFET devices, metal silicide layers for MOSFET devices, as well as methods of depositing metal layers. However none of the above prior art describe the novel features of the present invention in which a thin interlayer material, formed uniformly via a specific deposition procedure, is used to allow nickel silicide to be formed on MOSFET device regions at a temperature in which instability of nickel silicide does not occur.